In conventional serial communication interfaces that use oversampling during data reception (also referred to herein as oversampling serial communication interfaces), for example universal asynchronous receiver/transmitters (UARTs), the baud rate is typically obtained by dividing the base clock rate of the interface by a number that is an integer multiple of the oversampling factor. Thus, the possible baud rates are given by: base clock frequency/((oversampling factor)×(integer divisor)), where the oversampling factor is expressed, for example, in baud clock pulses (i.e., samples) per bit. If the base clock of the serial communication interface is set at a fixed frequency, as is typical, then there are significant gaps between the possible baud rates. For example, for a base clock frequency of 1.8432 MHZ and an oversampling factor of 16 pulses/bit, the baud clock rates produced by using integer divisors of 1,2 and 3 are 115,200 baud (bits/second in this example), 57,600 baud and 38,400 baud, respectively. Note the significant gap between the adjacent baud rates of 115,200 and 57,600. In this situation, if there is a need for a baud rate that does not fall near any of the available baud rates, for example 76,800, it is typically necessary to provide a higher base clock frequency, from which an acceptable approximation of the desired baud rate can be derived. However, the increased base clock frequency disadvantageously requires an increase in the power used by the serial communication interface.
It is therefore desirable to increase the number of available baud rates without increasing the base clock frequency of the serial communication interface.
The present invention provides for generation of a baud clock by dividing the base clock of the serial communication interface by one of a plurality of possible composite divisors. Each composite divisor is indicative of a minimum time interval between adjacent pulses of the associated baud clock, and further indicates that at least one pair of adjacent pulses within each symbol interval of the associated baud clock are to be separated by an extended time interval which is longer than the minimum time interval. The composite divisor advantageously results in a large number of available baud clock rates without increasing the base clock frequency.